Many asynchronous serial data modulation schemes are reliant upon pulse width (RZ—return to zero) or state width (NRZ—no return to zero) modulation. The most common modulation schemes rely upon discrimination between two or more pulse or state widths related by a specified multiplicative factor ‘n’. In order to demodulate such data streams, it has been common practice to extract a clock signal from the data stream with a period equal to, or an integer fraction of, the shortest transition width. For robust demodulation, this extracted clock signal must be phase locked to the data stream, which usually indicates the use of a phase-locked loop (PLL) design. Not only do PLLs bring complexity and additional cost to demodulator designs, they almost always employ fixed-frequency filters, and their performance is inversely proportional to bandwidth. This precludes their use in frequency-agile designs. There exists a need of a simple demodulation method for asynchronous serial data which facilitates wide frequency ranges.